A data interface for a memory circuit, such as a dynamic random access memory (DRAM), includes multiple signals. These signals can be transmitted via physical wires and input/output (I/O) circuits. Relative to other components, I/O circuits can be large in size and require chip size/die area. As a result, it can be advantageous to minimize the number of I/O circuits. In many memory standards the data interface includes the actual data bus (DQ), the data mask information (DM), and the data bit inversion information (DBI).
The data mask function can allow a data byte/word to be blocked from being written to a memory array. This operation can be useful to avoid time-expensive operations, such as READ-MODIFY-WRITE operations. Most DRAM standards (e.g., DDR 1 . . . 3 and GDDR4) require a dedicated pin DM per byte for the data mask function. In operation, the DRAM latches the data from the bus and the data mask, and later ignores the latched data information when determined that the mask bit is provided.
The data bit inversion function can be used to reduce the maximum power consumption involved in the transfer of data to the memory array. Similar to the data mask function, a dedicated pin DBI per byte is generally used for the DBI function. Different data bit inversion schemes can be used depending on whether the interface is terminated or unterminated.
In terminated interfaces, such as GDDR5, the Data Bit Inversion-Direct Current scheme (DBI-DC) may be used. Since current is flowing with a logical “0” rather than with a logical “1” DBI-DC minimizes the number of “0”s in a given data word. Thus, for example, if the number of logical “0” in a data word is five or more, the data its of the data word will be inverted and the DBI signal is asserted to indicate that the data has been inverted. In this manner, DBI-DC is able to reduce power consumption.
In unterminated interfaces, the Data Bit Inversion-Alternate Current scheme (DBI-AC) can be used. DBI-AC minimizes the number of toggling data lines. With DBI-AC encoding, the DBI pin signals to invert the data if more than half of the transferred data in a data word changed from one cycle to the next cycle. This DBI-AC encoding can reduce the average power consumption as well as the maximum peak currents, since less data lines need to be charged and discharged. In addition, this can limit the supply noise resulting from the inherent inductance of the DRAM and GPU package as well as from the dl/dt (current change over time).
FIG. 1 illustrates an exemplary implementation of a data write system supporting the data mask function and the data bit inversion function. The system can include a memory controller and a DRAM memory. The memory controller can pass a data word comprising 8 bits into a DBI encoder. The DBI encoder can determine whether the data word should be inverted. If inversion is appropriate, the DBI encoder can invert the data word and assert a DBI signal. The data word (in inverted form or not) can then be passed to the DRAM memory via data bus DQ and the DBI signal can be passed via the data line DBI. A separate DM signal can, be passes by the memory controller to the DRAM memory via data line DM.
The DBI decoder in DRAM memory can receive the data word and DBI signal. The decoder can invert the data word again depending on the DBI signal. The data word can then be written to the memory core. However, if the DM signal is asserted, the data word can be masked so that it is not written to the memory core.
FIGS. 2a and 2b are flow charts of exemplary processes for implementing the DBI-DC scheme and the DBI-AC scheme, respectively.
For DBI-DC as shown in FIG. 2a, logical output data, such as a data word, is passed into an encoder in the memory controller. The number of “0”s in the logical output data is determined. In this case, since the logical output data constitutes a data word, which is equal to a byte (or 8 bits) of data, it is determined whether there are more than four “0”s in the data word. If there are more than four “0”s, the data is inverted and the /DBI signal is driven low. Note that in this case the /DBI signal is an active low signal (i.e., a logical “1” is represented by a low voltage rather than by a high voltage). On the other hand, if there are four or less “0”s, the data is not inverted and the /DBI signal is driven high.
When the data word and the /DBI signal are received by the DRAM memory, it is determined whether the data word has been inverted by looking at the /DBI signal. If the /DBI signal is a logical “0”, it is determined that the data word was inverted and so the data word is inverted again. If the /DBI signal is a logical “1”, it is determined that the data word was not inverted and so the data word is left alone. The data word (whether inverted or not) is then written to the DRAM memory.
For DBI-AC as shown in FIG. 2b, logical output data, such as a data word, is passed into an encoder in the memory controller. The number of signal transitions on data lines for the current data word (current cycle) with respect to the previously transmitted data word (previous cycle) is determined. In this case, since the logical output data constitutes a data word, which is equal to a byte (or 8 bits) of data, it is determined whether there are more than four changing data line signals from the previous cycle to the current cycle. If there are more than four transitions, the data is inverted and the DBI signal is driven high. If there are four or less transitions, the data is not inverted and the DBI signal is driven low.
When the data word and the DBI signal are received by the DRAM memory, it is determined whether the data word has been inverted by looking at the DBI signal. If the DBI signal is a logical “1”, it is determined that the data word was inverted and so the data word is inverted again. If the DBI signal is a logical “0”, it is determined that the data word was not inverted and so the data word is left alone. The data word (whether inverted or hot) is then written to the DRAM memory.
FIGS. 3 and 4 illustrate exemplary circuit components for implementing the DBI encoder according to the DBI-DC scheme and the DBI-AC scheme, respectively.
In FIG. 3, the data word is fed into a counter and an XOR gate. When determined that the data word includes more than four “0”s, the counter outputs a logical “1” which is fed into the XOR gate and a NOT gate. This results in the bits of the data word being inverted by the XOR gate and the /DBI signal being asserted (according to the active low paradigm). When determined that the data word includes our or less “0”s, the counter outputs a logical “0” which is fed into the XOR gate and the NOT gate. This results in the bits of the data word staying the same and the /DBI signal not being asserted.
In FIG. 4, the data word is fed into a counter and an XOR gate. Also fed into the counter is the data word transmitted in the previous cycle (thus, the data word in its inverted state if it was inverted, or in its non-inverted state if it was not inverted). When determined that there are more than four transitions, the counter outputs a logical “1” which is fed into the XOR gate and is output as the DBI signal. This results in the bits of the data word being inverted by the XOR gate and the DBI signal being asserted (according to the active high paradigm). When determined that there are four or less transitions, the counter outputs a logical “0” which is fed into the XOR gate and is output as the DBI signal. This results in the bits of the data word staying the same and the DBI signal not being asserted.
FIGS. 5a and 5b illustrate exemplary circuit components for implementing the DBI decoder according to the DBI-DC scheme and the DBI-AC scheme, respectively.
In FIG. 5a, the transmitted data word is received and fed into an XOR gate. The /DBI signal is received and fed into a NOT gate, the output of which is then also fed into the XOR gate. The XOR gate appropriately inverts or doesn't invert the data word, which is then written to the memory core. The circuit according to FIG. 5b operates in a similar fashion except that a NOT gate is not required since the DBI signal follows the active high paradigm.
In short, the above described systems require 10 data lines/pins per byte of data to accommodate both a data bit inversion function and a data mask function (i.e., eight lines/pins for the data word, one line/pin for the DBI signal, and one line/pin for the DM signal). This represents a 25% line/pin overhead relative to the amount of data being transferred.